Senior GPU System Architect, Context Management and Register Architecture

NVIDIA is seeking a Senior System Architect to define two foundational areas of the GPU: the mechanisms that manage GPU execution state and the register address and access architecture used across the processor. This hands-on role spans architecture, functional modeling, verification, hardware and software integration, and silicon bring-up. We collaborate across ASIC, firmware, driver, verification, and performance teams to guide features from early exploration through implementation and validation. The resulting architecture will build GPU responsiveness, reliability, scalability, software compatibility, and the way increasingly sophisticated processors are configured and managed.

What you’ll be doing:

• Architect and evolve GPU context-management mechanisms, including efficient methods for saving and restoring execution state.
• Own the GPU-wide register address map, coordinate address allocation, resolve conflicts, and maintain a scalable architecture through multiple product iterations.
• Define requirements, interfaces, compatibility expectations, and on-die and cross-die interconnects for register access and programming.
• Develop C++ functional-model support and collaborate with hardware build, embedded software, device software, testing, and performance groups to translate architectural requirements into coordinated solutions.
• Evaluate tradeoffs across performance, area, complexity, scalability, reliability, compatibility, and development effort.
• Build validation strategies, debug cross-stack issues through pre-silicon validation and initial silicon testing, and improve the tools and automation supporting register-interface development.

What we need to see:

• A bachelor’s degree in Computer Engineering, Computer Science, Electrical Engineering, or a similar field, or equivalent experience.
• 5+ years of proven experience in computer architecture, GPU architecture, CPU architecture, system-on-chip design, or a related area.
• Experience designing, modeling, or validating sophisticated hardware features from definition through confirmation, with proficiency in C++ and Python or a comparable scripting language.
• Strong understanding of interactions among hardware, firmware, and system software, with a demonstrated ability to diagnose and resolve issues spanning components or abstraction layers.
• Experience developing coherent architectural standards across multiple teams, paired with clear technical writing skills and experience crafting specifications and collaborating with distributed, cross-functional groups.

Ways to stand out from the crowd:

• Experience with hardware register architecture, address-map development, memory-mapped I/O, or device-control interfaces.
• Knowledge of context switching, scheduling, virtualization, or execution-state management.
• Familiarity with RISC-V or other embedded-controller architectures, on-chip interconnects, or cross-die communication fabrics.
• Experience with firmware, device drivers, functional or performance modeling, hardware verification, or test development.
• Hands-on experience with pre-silicon validation, silicon bring-up, automated interface generation, or maintaining architectural compatibility across product generations.

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You will also be eligible for equity and benefits.

This posting is for an existing vacancy. 

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